Memory(52)<= «000»& «000000»& «0000000»& «0000000»& «0000»& «0»; - any value

Memory(53)<= «000»& «000000»& «0000000»& «0000000»& «0000»& «0»; - any value

Memory(54)<= «000»& «000000»& «0100000»& «0000000»& «0000»& «0»; - IncPC

Memory(55)<= «000»& «000000»& «0001000»& «0000000»& «0000»& «0»; - MarIn

Memory(56)<= «000»& «000000»& «0000110»& «0000000»& «0000»& «0»; - RdWr, CS

Memory(57)<= «000»& «000000»& «0000001»& «0000000»& «0000»& «0»; - MbrIn

Memory(58)<= «000»& «000000»& «0000000»& «1000000»& «0000»& «0»; - MbrOut

Memory(59)<= «001»& «000000»& «1000000»& «0000000»& «0000»& «0»; - Instr2, PCIn

process(RD)

begin

if RD='1' and RD'event then

InstrCom<=Memory (CONV_INTEGER ('0'& Adr));

MrOut<='1';

end if;

if RD='0' and RD'event then MrOut<='0';

end if;

end process;

end Memory;

Временная диаграмма работы памяти УУ Memory:

VHDL - описание остальных элементов схемы (регистра CAR и регистра СBR, регистра инструкций, мультиплексора, декодера, простых логических элементов, регистров MAR и MBR):

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity CAR is

port (D: in std_logic_vector (5 downto 0);

CarIn: in std_logic;

CarOut: out std_logic;

Q: out std_logic_vector (5 downto 0));

end CAR;

architecture CAR of CAR is

begin

process(CarIn)

begin

if CarIn='0' and CarIn'event then

Q<=D;

CarOut<='1';

end if;

if CarIn='1' and CarIn'event then CarOut<='0';

end if;

end process;

end CAR;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity CBR is

port (InstrCom: in std_logic_vector (0 to 27);

CbrIn: in std_logic;

Adr: out std_logic_vector (5 downto 0);

Instr0: out std_logic;

Instr1: out std_logic;

Instr2: out std_logic;

PCIn: out std_logic;

IncPC: out std_logic;

IrIn: out std_logic;

MarIn:out std_logic;

RdWr:out std_logic;

CS:out std_logic;

MbrIn:out std_logic;

MbrOut:out std_logic;

MbrInD:out std_logic;

MbrOutD:out std_logic;

RzIn:out std_logic;

RzOut:out std_logic;

Inv:out std_logic;

RAIn:out std_logic;

RIn:out std_logic;

ROut:out std_logic;

RDCIn:out std_logic;

SADD:out std_logic;

InvZ: out std_logic);

end CBR;

architecture CBR of CBR is

begin

process(CbrIN)

begin

if CbrIN='1' and CbrIN'event then

Instr0<=InstrCom(2) after 1ns;

Instr1<=InstrCom(1) after 1ns;

Instr2<=InstrCom(0) after 1ns;

ADR<=InstrCom (3 to 8) after 1ns;

PCIn <=InstrCom(9) after 1ns;

IncPC<=InstrCom(10) after 1ns;

IrIn <=InstrCom(11) after 1ns;

MarIn <=InstrCom(12) after 1ns;

RdWr <=InstrCom(13) after 1ns;

CS <=InstrCom(14) after 1ns;

MbrIn<=InstrCom(15) after 1ns;

MbrOut<=InstrCom(16) after 1ns;

MbrInD<=InstrCom(17) after 1ns;

MbrOutD<=InstrCom(18) after 1ns;

RzIn <=InstrCom(19) after 1ns;

RzOut<=InstrCom(20) after 1ns;

Inv<=InstrCom(21) after 1ns;

RAIn<=InstrCom(22) after 1ns;

RIn <=InstrCom(23) after 1ns;

ROut<=InstrCom(24) after 1ns;

RDCIn <=InstrCom(25) after 1ns;

SADD<=InstrCom(26) after 1ns;

InvZ<=InstrCom(27) after 1ns;

end if;

end process;

end CBR;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity IR is

port (Command: in std_logic_vector (7 downto 0);

IRin: in std_logic;

Reset: in std_logic;

IrOut: out std_logic;

Com: out std_logic_vector (7 downto 0));

end IR;

architecture IR of IR is

begin

process (IrIn, Reset)

begin

if IrIn='1' and Irin'event then

Com<=Command after 2ns;

IrOut<='1'after 2ns;

end if;

if IrIn='0' and Irin'event then IrOut<='0';

end if;

if Reset='1' then

Com<= «00000000»;

IrOut<='1';

end if;

end process;

end IR;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity DC1 is

port (Ale:in std_logic;

Com: in std_logic_vector (7 downto 0);

ComAdr: out std_logic_vector (5 downto 0));

end DC1;

architecture DC1 of DC1 is

begin

process(Ale)

begin

if Ale='1' and Ale'event then

if Com= «00000000» then ComAdr <= «000111»;

elsif Com= «00000001» then ComAdr <= «001110»;

elsif Com= «00000010» then ComAdr <= «011011»;

elsif Com= «00000011» then ComAdr <= «100111»;

elsif Com= «00000100» then ComAdr <= «110011»;

else ComAdr <= «000000»;

end if;

end if;

end process;

end DC1;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity INV is

port (DIn: in std_logic_vector (7 downto 0);

Inv: in std_logic;

DOut: out std_logic_vector (7 downto 0));

end INV;

architecture INV of INV is

begin

DOut<=not DIn when Inv='1'else DIn;

end INV;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity LogAnd is

port (in1: in std_logic;

in2: in std_logic;

Sout: out std_logic);

end LogAnd;

architecture LogAnd of LogAnd is

begin

Sout<=in1 and in2 after 1ns;

end LogAnd;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity LogOR is

port (in1: in std_logic;

in2: in std_logic;

SOut: out std_logic);

end LogOR;

architecture LogOR of LogOR is

begin

SOut<=in1 or in2 after 1ns;

end LogOR;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity MUX is

port (IN1: in std_logic_vector (5 downto 0);

IN2: in std_logic_vector (5 downto 0);

IN3: in std_logic_vector (5 downto 0);

Adr0: in std_logic;

Adr1: in std_logic;

CLK: in std_logic;

MuxOut: out std_logic;

OUT1: out std_logic_vector (5 downto 0));

end MUX;

architecture MUX of MUX is

begin

process(CLK)

begin

if CLK='1' and CLK'event then

if Adr1='0' and Adr0='0' then OUT1 <= IN1;

elsif Adr1='1' then OUT1 <= IN2;

elsif Adr1='0' and Adr0='1' then OUT1 <= IN3;

else Out1<= «000000»;

end if;

MuxOut<='1';

end if;

if CLK='0' and CLK'event then MuxOut<='0';

end if;

end process;

end MUX;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity MAR is

port (RST: in std_logic;

CLK: in std_logic;

MarIn: in std_logic;

AdrIn: in std_logic_vector (7 downto 0);

AdrOut: out std_logic_vector (7 downto 0));

end MAR;

architecture MAR of MAR is

signal reg: std_logic_vector (7 downto 0):= «00000000»;

begin

process (CLK, RST)

begin

if CLK='0' and CLK'event and MarIn='1' then reg<=AdrIn;

end if;

if CLK='1' and CLK'event then AdrOut<=reg;

end if;

if RST='1' then reg<= «00000000»;

end if;

end process;

end MAR;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity MBR is

port (RST: in std_logic;

CLK: in std_logic;

MbrIn: in std_logic;

MbrOut: in std_logic;

MbrInD: in std_logic;

MbrOutD: in std_logic;

DataIn: inout std_logic_vector (7 downto 0);

DataOut: inout std_logic_vector (7 downto 0));

end MBR;

architecture MBR of MBR is

signal reg: std_logic_vector (7 downto 0);

begin

Process (CLK, RST)

begin

if CLK='0' and CLK'event then

if MbrIn='1' then reg<=DataIn;

elsif MbrOut='1' then DataOut<=reg;

elsif MbrInD='1' then reg<=DataOut;

elsif MbrOutD='1' then DataIn<=reg;

end if;

if MbrIn='0' and MbrOutD='0' then DataIn<= «ZZZZZZZZ»;

end if;

if MbrOut='0' and MbrInD='0' then DataOut<= «ZZZZZZZZ»;

end if;

end if;

if RST='1' then reg<= «00000000»;

end if;

end process;

end MBR;

-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity RZ is

port (DIn: in std_logic_vector (7 downto 0);

CLK: in std_logic;

RST: in std_logic;

RZOut: in std_logic;

RZIn: in std_logic;

InvZ: in std_logic;

DOut: out std_logic_vector (7 downto 0));

end RZ;

architecture RZ of RZ is

signal regist: std_logic_vector (7 downto 0);

begin

process (CLK, RST)

begin

if CLK='0' and CLK'event and RZIn='1' then regist<=DIN;

end if;

if CLK='0' and CLK'event and RZOut='1' then

if InvZ='1'then DOut<=not regist after 3 ns;

else DOut<=regist after 3 ns;

end if;

end if;

if CLK='0' and CLK'event and RZOut='0' then DOut<= «ZZZZZZZZ» after 3 ns;

end if;

if RST='1' then regist<= «00000000»;

end if;

end process;

end RZ;

7. Тестирование процессора и подтверждение правильности его работы с помощью временных диаграмм

Описание процессора на языке Active VHDL:

library IEEE;

use IEEE.std_logic_1164.all;

entity MPA is

port (CLK: in STD_LOGIC;

Reset: in std_logic;

FC, bit_out: out std_logic;

DataBus: inout std_logic_vector (7 downto 0));

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